1. Field of the Invention
The invention concerns OTP or one time programmable memories.
2. Description of the Prior Art
These memories are EPROMS, namely electrically programmable non-volatile memories. However, unlike standard EPROMs which are provided with a window that is transparent to ultra-violet rays and which can be erased, through this window, by ultra-violet rays, and then reprogrammed electrically, OTP memories are encapsulated in an opaque package which is not transparent to ultra-violet rays. Once programmed, they can no longer be erased.
More precisely, each bit of the memory is initially in a non-programmed state. If it is programmed, it means that its state is changed, and the first state can no longer be returned to.
Most usually, each memory cell is formed by a transistor having a control gate and a floating gate. Through adequate biasing of the source, the drain and the control gate, this transistor can be programmed. This means that its floating gate is charged permanently. If the transistor is in its initial "non-programmed" state, it can be easily made conductive by a read voltage applied to its control gate. If it is in the "programmed" state (i.e. with its floating gate filled with electrons), it can no longer be made conductive by the same read voltage applied to its control gate.
It will be easily understood that it is very difficult to test memories of this type, at any rate after they have been encapsulated in their final, opaque package. For, they can no longer be programmed to be tested. They have to be sold in a blank state without any information, i.e. they can be marketed only in an non-programmed state, and the purchaser does the programming to place the information that he desires thereon. If there is no information in the memory, it is clearly impossible to perform certain tests on the exactness of the information stored, or on the quality of the access paths to this information. However, the purchaser would like to have guarantees on the product that he is going to purchase, and it would be desirable to perform certain tests.
For example, one useful test is a speed test wherein a check is made on the period that elapses between the instant when an address of the memory is designated and the instant when the information stored at this address is received at the output.
This test becomes highly imprecise if it is performed on a memory, all the transistors of which are in the non-programmed state. For, an attempt will be made to successively address different memory cells at very short intervals, and to ascertain the length of time at the end of which the information is received at output. However, since the information will always be the same, regardless of the cell addressed, there will be no real distinction made between the end of the preceding piece of information and the start of the following piece of information.
Besides, this is why, in non-OTP memories, speed tests are conducted on speed by recording a "checkerboard pattern" of information in the memory, i.e. every other transistor is programmed, and the successive addresses of the memory are read at great speed: the output information will alternately be a logic "0" and a logic "1", and it will be easy to check the maximum speed of access to the memory cells.
This access speed is notably limited by the memory's row and column decoding circuits, the input and output amplifiers, etc.
The present invention proposes a means to facilitate the testing of one time programmable memories, notably speed testing, but also the testing of faults in decoding circuits and of certain parts of the network of cells of the memory.
According to the invention, since the memory cells cannot be programmed to check the behaviour of the memory containing programmed cells and non-programmed cells, it is proposed to simulate programmed memory cells by non-programmed memory cells, for which the addressing in read mode will have been inhibited, to make it look as if they are programmed. This concept could be stated in another way: if a particular memory cell is designated by means of a read voltage applied by a decoder to this memory cell, and if the state of the memory cell is read on a column conductor, there are two possibilities: either the memory cell is not programmed and the transistor that forms it will give a current showing that it is effectively not programmed, or else the memory cell is programmed and then it can no longer be made conductive by the read voltage applied by the decoder, and in this case, no current flows or is detected on the column conductor. But then, if no current is detected, the column conductor behaves exactly as if the memory cell were not at all addressed. It behaves as if it did not receive the read voltage coming from the decoder or as if it were not connected to the output of the memory.
The idea of the invention therefore consists in:
applying, to a decoder, successive addresses of the memory cells to be tested; PA1 making the decoder apply a read voltage to these cells so that, at the output of the memory, they give a piece of information on their state; PA1 inhibiting the read process when certain memory cells are designated by the decoder so that these points behave, when seen from the output, like cells which are in a different state from the state in which they actually are; during this inhibition, the decoder addresses no additional memory cells which would be reserved for the test.
The inhibition of the reading operation may consist in preventing the application of a read voltage to the designated memory cells or, again, in preventing the information read at the column from being transmitted to the output of the memory.
Thus, all the cells which shall be designated by inhibited addressing signals could be considered to be programmed cells of the memory, whereas they are not so in reality.
Thus, a simulation is made of the desired contents of a memory, all the cells of which are, in fact, in the same non-programmed state, and the behaviour of the memory for which the contents are thus simulated is observed.
For example the contents, in checkerboard pattern, of a memory will be simulated by inhibiting the transmission of the address signals to the memory cells for one cell out of two, and in permitting it for the following cell. It is also possible to simulate other patterns than a checkerboard pattern, the simplest pattern being one of alternating rows of programmed cells and non-programmed cells. More complicated patterns can be envisaged without any difficulty in theory, but they would necessitate additional, specific decoding circuits in the memory integrated circuit, and the more complicated the pattern, the greater would be the space occupied by these additional, specific decoding circuits. Hence, they will not be used to excess.
For, it is the integrated circuit, comprising the memory, that will include specific auxiliary circuits enabling this simulation of memory contents during the test.